An electronic circuit is chemically and physically integrated into a substrate, such as a silicon wafer by patterning regions in the substrate, and by patterning layers on the substrate. These regions and layers can be conductive, for conductor and resistor fabrication, or insulative, for insulator and capacitor fabrication. They can also be of differing conductivity types, which is essential for transistor and diode fabrication.
Degrees of resistance, capacitance, and conductivity are controllable, as are the physical dimensions and locations of the patterned regions and layers, making circuit integration possible. Fabrication can be quite complex and time consuming, and therefore expensive. It is thus a continuing quest of those in the semiconductor fabrication industry to reduce fabrication times and costs of such devices in order to increase profits. Any simplified processing step or combination of processes at a single location becomes a competitive advantage.
A common requirement in integrated circuit (IC) fabrication is the etching of a "sandwich" structure such as a layer of silicon dioxide ("oxide") over a layer of polycrystalline silicon ("poly") over a layer of thin oxide (often called "gate oxide", because of its frequent use in transistor gates). Oxide is an insulator with dielectric properties. Poly is resistive in nature, but is made less resistive when doped with an element, such as phosphorus, having less or more than 4 valence electrons.
Two basic types of etch techniques can be used; chemical or "wet", and plasma or "dry". Etch chemistries for oxide and for poly are well known. Ordinarily, a mask layer is first deposited on a layer to be etched, and a mask opening made in the mask layer by photolithographic means, exposing a portion of the layer to be etched. An appropriate etch technique and chemistry is employed, which acts only on the exposed portion.
Difficulties may arise when more than one layer is desired etched at a single site because of different requirements for each: an etch chemistry for the bottom layer may interfere with a layer already etched through and exposed along the sidewall. Often these difficulties require changes between wet and dry techniques, and different types of etchers.
It is desirable to etch multiple layers at a single processing site. Less handling of the IC is required, which reduces handling errors, as well as the number of particle caused defects. Less masking steps may also be required, which directly reduces fabrication costs.
Both oxide and poly can be etched in a single parallel plate plasma reactor chamber. However, an oxide is typically etched in fluorine deficient fluorocarbon based plasmas, whereas poly is often etched in fluorine or chlorine based plasmas. Reactor electrode materials may also differ.
If a single-chamber process were attempted using conventional art to etch an oxide/poly sandwich structure, the erodible electrode required for oxide etch would be destroyed by the poly etchants. Using conventional methods, the two steps are not profitably compatible.
Some current manufacturing processes etch the oxide/ poly/oxide structure in three separate etch chambers. Such technology involves etching the top oxide layer in an oxide etch chamber, then moving the wafer to a poly etch chamber for the poly etch, and then again moving the wafer back to the oxide chamber to etch the last oxide layer.
It is therefore desirable to etch an oxide/poly/oxide sandwich "in situ", that is, performing all required steps within a single etch chamber, under continuous vacuum conditions, in the same process run.
The following patents describe in situ etch processes of various conductive and insulative materials: U.S. Pat. No. 4,939,105 to Langley; U.S. Pat. No. 5,013,398 to Long, et al.; U.S. Pat. No. 5,094,712 to Becker, et al.; and U.S. Pat. No. 5,271,799 to Langley, all assigned to Micron Technology, Inc. The above-cited patents are all very worthwhile, describing anisotropic methods of etching.
The process of the present invention is also useful in etching contacts for metalization. The process of the present invention further provides for an isotropic polysilicon etch.
The polysilicon (which is a conductor) is undercut to provide some margin in which to place an insulating material, such as a nitride, thereby separating the polysilicon from the conductive material which is subsequently disposed in the contact hole created by the process of the present invention.
One embodiment of process of the present invention also includes a selective oxide to nitride etch chemistry (See also, "A Method of Obtaining High Oxide to Nitride Selectivity in an MERIE Reactor," Electrochemical Society. Inc. Conference, May 1993, authored by the inventors of the present application, as well as U.S. Pat. No. 5,286,344, issued to Blalock et al, and assigned to Micron Technology).